(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices and more particularly, to a method of creating a network of air gaps that is located in a layer of Inter Metal Dielectric of a semiconductor device.
(2) Description of the Prior Art
The increased device density that is part of semiconductor device fabrication leads to the placing of numerous devices on one monolithic substrate. The individual devices are electrically isolated from each other and are interconnected to other semiconductor devices of the total package to perform certain desired circuit functions. Decreased device dimensions result in a reduction of electrical energy that can be stored in a device. This reduction of device size further results in a reduction of the internal device capacitances such as parasitic capacitances at source and drain regions of a gate electrode of MOS devices. At these reduced devices capacitances, the relative parasitic capacitance of the device interconnect lines become more important in the design of the semiconductor device and in the ability of the device to perform the required functions at the required frequency and the required power level. The interconnect capacitance becomes an important fraction of the capacitance of each circuit, an effect that is especially pronounced as the operating frequency of the device is increased. With more device function packed in smaller device geometry, more signal lines are in closer physical proximity than ever before resulting in an increased impact of parasitic capacitances of the signal lines. This problem of interconnect parasitic capacitance must therefore be addressed whereby processes or solutions that result in reducing this capacitance are the objective.
Coupling capacitances between adjacent lines are dependent on a number of factors such as the length of the lines, the proximity of the lines and the distance over which the lines runs adjacent to lines in close proximity. Longer lines result in increased capacitive coupling, as does closer proximity between lines. Of equal importance in determining the capacitive coupling that occurs between adjacent lines is the material that is used to separate adjacent lines. Materials (that are used between adjacent lines) that have a high dielectric constant increase the capacitive coupling between the adjacent lines while materials with low dielectric constant decrease the capacitive coupling between adjacent lines. It is therefore important to select materials (dielectrics) that are used to separate interconnect lines that have as low a dielectric constant as possible. Conventional semiconductor fabrication typically uses silicon dioxide as a dielectric; this has a dielectric constant of about 3.9. Other examples are silicon with a dielectric constant of 11.7, silicon nitride with a dielectric constant of 7.0, Spin-On-Glass with a dielectric constant of 4.0. All of these examples are of dielectric materials that have a dielectric constant that is too high for application with sub-micron device feature sizes and that would impose serious limitations on device performance both in the frequency range in which the device can be used and in the power or switching level of the device. For high frequency operation, power consumption increases proportionally with frequency. For a given interconnect layout, both power consumption and crosstalk decrease, and performance increases, as the dielectric constant of the insulator decreases.
The use of many of the low dielectric constant materials, such as aerogel with a dielectric constant of 1.2, is not feasible due to the fact that equipment is not available to properly process the new dielectric material in various integrated circuits or because these materials require critical steps of processing which significantly increase the manufacturing cost. Also, the chemical or physical properties of many low dielectric constant materials are usually difficult to make compatible with or integrate into conventional integrated circuit processing. For instance, aerogel requires a very sensitive drying step that is not well suited for a high volume, low cost process of semiconductor device manufacturing.
The lowest possible and therefore the ideal dielectric constant is 1.0, this is the dielectric constant of a vacuum whereas air has a dielectric constant of slightly larger than 1.0.
The formation of air gaps between conducting lines of high speed Integrated Circuits (IC's) is typically a combination of the deposition of a metal layer, selective etching of the metal layer to form the desired line patterns, the deposition of a porous dielectric layer or a disposable liquid layer which is then selectively removed to form the desired air-gaps.
The presence of a high level of capacitive coupling between adjacent signal lines can result in an increase of capacitive crosstalk between adjacent conductor lines of a semiconductor circuit, that is the voltage on a first conductor line alters or affects the voltage on a second conductor line. This alteration in voltage can cause erroneous voltage levels in the Integrated Circuit making the IC increasingly prone to faulty operation. It becomes therefore imperative to reduce the resistance capacitance (RC) time constant and the crosstalk between adjacent conducting lines.
The invention addresses the creation of air gaps that are created in a layer of Inter Metal Dielectric (IMD). For Prior Art applications of a layer of IMD, the layer of IMD has to be thick in order to significantly reduce crosstalk and the RC delay of the adjacent metal lines. However, this thickness by its very nature limits the aspect ratio of the contact openings that can be established in the layer of IMD, which is contrary to the requirement of sub-micron device features. In addition, dielectric materials that have the required low-k value do not have the mechanical strength to support overlying device features if high aspect ratio openings are created in the dielectric. It is therefore required to provide a method that reduces the capacitive coupling through the layer of IMD while at the same time providing a mechanically stable support structure within the semiconductor device.
U.S. Pat. No. 5,828,121 (Lur et al.) shows an air gap between metal lines at different levels by etching the dielectric layers between the metal line levels. This is close to the invention.
U.S. Pat. No. 5,783,864 (Dawson et al.) shows air gaps and pillars between metal layers. This is close to the invention.
U.S. Pat. No. 5,561,085 (Gorowitz et al.) shows a method for forming air gap bridges.
U.S. Pat. No. 5,461,003 (Havemann et al.) and U.S. Pat. No. 5,527,137 (Jeng) show other air gap processes.
U.S. Pat. No. 5,908,318(Wang et al.) shows an air gap in an ILD by etch out.